During the design stage of processors, verification is necessary to ensure that all possible combinations of instructions and execution lengths are implemented properly and are tested by the simulation environments. The verification of the processor design relies on logic design to provide a list of all existing combinations and adds coverage events for these combinations to simulation environments and also ensures that all events are covered. However, this method requires substantial manual and error-prone work, the provided list may be incomplete or incorrect, and logic changes require the addition and/or removal of coverage events.
State-of-the-art hardware implementations of execution units, such as fixed point units (FXUs) and floating point units (FPUs), support a high number of instructions/operations. For example, a modern floating point unit (FPU) implements several hundred instructions. Each instruction can have different execution lengths, measured in cycles. For the most part, the number of cycles necessary to execute an instruction depends upon the specific input operands. Implementations may detect so-called early-out cases that do not require the execution of the complete computational algorithm. For example, multiply-by-zero and divide-by-one operations both result in well-defined values. Furthermore, hardware settings such as the setting of switches that enable or disable certain functionality and the specific circumstances of executing an instruction, such as forwarding results from previous instructions, can influence the execution length of an instruction as well. Furthermore, performance improvements of existing instruction implementations require an efficient method to track changes and their effects.
The increasingly high number of instructions supported by current execution unit implementations and their various execution lengths makes it very difficult to ensure that all possible combinations of instructions and execution lengths are implemented properly, function as intended, and are fully covered in the simulation environments.